1. Field of the Invention
The present invention relates to an apparatus for driving SRAM cell, and more particularly to techniques which effectively drive the SRAM with a stable data latch operation.
2. Description of Related Art
Referring to FIG. 1 in which a conventional SRAM cell is shown, source terminals of drive transistors 101 and 102 are connected to a ground voltage level GND, and drains thereof are respectively connected to cell nodes N1 and N2 in which data is stored. Accesses transistors 111 and 112 are formed between bit lines BIT and /BIT and the cell nodes N1 and N2, respectively, such that they access the stored data in response to control signals on a word line WL. PMOS transistors 121 and 122 connected to the nodes N1 and N2 act as high load resistors.
However, the conventional SRAM cell has drawbacks in that an unstable voltage change can be caused by a bit line precharge while the access transistors 111 and 121 coupled to the word line WL are turned on. Because the bit lines BIT and /BIT are precharged up to a given voltage level (power supply), positive charges on the bit lines can be introduced to the cell nodes N1 and N2 during the bit line enable and this charge transfer between the bit lines and cell nodes may increase the voltage level of the cell nodes N1 and N2.
On the other hand, in the case where the power supply is low, the high node of the nodes N1 and N2 may be in a relatively low voltage level. For example, assuming that the power supply is in a relatively low voltage level and the node N1 must be in relatively high voltage level, this low power supply makes the voltage level of the cell node N1 relatively low. This low voltage level in the cell node N1 makes the current of the drive transistor 102 decreased. Also, the decreased current of the drive transistor 102 increases the voltage of the node N2 and the increased voltage of the node N2 weakly turn on the drive transistor 101. As a result, the high cell node N1 can not be kept its voltage level high. Accordingly, the voltage difference between the nodes N1 and N2 is decreased. Further, at a low temperature, because of the increase of the threshold voltage of the drive transistors, this low-voltage difference is getting more serious. At this low power supply, since the voltage difference between the nodes N1 and N2 is low, the memory cell is sensitive to a noise and the cell current is decreased, so that the memory cell operation may be unstable and the time the cell data is read out on the bit line is delayed.
FIGS. 2A and 2B are plots illustrating the transient voltage analysis in the SRAM of FIG. 1. In particular, FIG. 2A is a simulation plot in the case where the power supply is 2.5 V and FIG. 2B is a simulation plot in the case where the power supply is 2.0 V. Referring to FIGS. 2A and 2B, the voltage difference between the nodes N1 and N2 is 1.31 V and 0.45 V at the power supply 2.5 V and 2 V, respectively. That is, the lower the power supply is, the lower the voltage difference is.
With the decreasing trend of the power supply, for example, from 5 V to 3.3 V or 3.3 V to 2.2 V, the conventional SRAM has a problem in that the cell data latch is unstable.